1. Field of the Invention
The present application relates generally to a design structure and more specifically, to a design structure for a programmable interpolative voltage controlled oscillator with adjustable range.
2. Background of the Invention
A voltage-controlled oscillator (VCO) is an electronic oscillator specifically designed to be controlled in oscillation frequency by a voltage input. The VCO is a circuit that generates an oscillating signal at a frequency controlled by a voltage supplied from an external source. The frequency of oscillation, or rate of repetition, is varied with an applied DC voltage, while modulating signals may be fed into the VCO to generate frequency modulation (FM), phase modulation (PM), and pulse-width modulation (PWM). VCOs are basic building blocks of many electronic systems and may be found in computer disk drives, wireless electronic equipment, such as cellular telephones, and other systems having an oscillation frequency controlled by an applied tuning voltage. One typical use of a VCO is in phase-locked loops (PLLs) of integrated circuit devices.
A phase-locked loop (PLL) is a closed loop feedback control system that generates an output signal in relation to the frequency and phase of an input, or reference, signal. The PLL automatically responds to the frequency and phase of the input signal by raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. PLLs are widely used in computing devices, telecommunications systems, radio systems, and other electronic applications where it is desired to stabilize a generated signal or to detect signals in the presence of noise. Since an integrated circuit can hold a complete PLL, the use of PLLs in modern electronic devices is widespread.
PLLs generally include a phase detector circuit, a low pass filter circuit, and a VCO placed in a negative feedback configuration. In addition to these elements, a frequency divider circuit may be provided in the feedback path, the reference signal path, or both, in order to make the PLL's output signal an integer multiple of the reference signal. The phase detector compares the phase of two inputs and outputs a corrective signal to control the VCO such that the phase difference between the two inputs becomes zero. The two inputs are a reference signal and the divided output of the VCO.
Various types of phase detector circuits are known including simple XOR gates, four-quadrant multiplier (or “mixer”) circuits, proportional phase detector circuits, and the like. A more complex phase detector uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency. This type of phase detector circuit is known as a phase frequency detector (PFD).
The VCO is used to generate a periodic output signal. For example, if the VCO is at approximately the same frequency as the reference signal, and if the phase of the VCO falls behind the phase of the reference signal, the phase detector circuit causes a charge pump of the PLL to charge the control voltage so that the VCO speeds up. Likewise, if the phase of the VCO progresses ahead of the phase of the reference signal, the phase detector circuit causes the charge pump to change the control voltage to slow down the VCO. The low-pass filter smoothes out the abrupt control inputs from the charge pump. Since the frequency of the VCO may be far from the frequency of the reference signal, practical phase detectors may also respond to frequency differences, such as by using a phase frequency detector (PFD), so as to increase the lock-in range of allowable inputs.
As discussed above, most PLLs also include a frequency divider circuit between the VCO and the feedback input to the phase detector circuit in order to produce a frequency synthesizer. This frequency divider circuit may be programmable so as to achieve different output or feedback frequencies of the output signal. Some PLLs may also include a frequency divider circuit between the reference clock input and the reference input to the phase detector circuit. If this frequency divider circuit divides the frequency of the reference signal by M, the inclusion of this frequency divider circuit between the reference clock input and the reference input to the phase detector circuit allows the VCO to multiply the reference signal's frequency by N/M, where N is the multiplier provided by the VCO.
There are a number of different designs for VCOs that are generally known in the art. One basic design for a VCO is the ring oscillator. Ring oscillators have a number of delay stages of amplifiers wherein the amount of delay of each stage is controlled by an input voltage or current. The frequency can be further controlled by varying the capacitance of each stage. The output of the Nth stage is coupled to the input of the first stage. The ring oscillator's frequency is inversely proportional to twice the total delay. Very high frequencies can be obtained with ring oscillators by decreasing the delay and decreasing the number of delay stages, but the oscillators are susceptible to noise and jitter. Ring oscillators, depending on the phase noise requirement, typically require much less power and area than known inductor-capacitor (LC) oscillators or multi-vibrator oscillators.
FIG. 1 shows a typical ring voltage controlled oscillator 130 in which a number of delay stages 142, 144, 146 drive each other in a ring to achieve oscillation. Load capacitors 152, 154, 156 on the output of each delay stage can be varied to tune the ring, such as in U.S. Pat. No. 5,191,301 entitled “Integrated Differential Voltage Controlled Ring Oscillator,” issued to Mullgrav on Mar. 2, 1993, assigned to the same assignee as the present application, and herein incorporated by reference in its entirety.
The frequency of oscillation can be stated as: F=½[N(Td+Tc)]−−1 where Td is the fixed time delay per stage which represents the wiring and parasitic capacitance, Tc is the capacitor variable time delay per stage, and N is the number of delay stages 142, 144, 146. Tc varies as the capacitance values of load capacitors 152, 154, 156 are varied. In this arrangement, large tuning ranges can be achieved with large capacitor variations. In order to get a 2:1 frequency range, for example, Tc must be equal to Td, i.e., for each stage, the fixed time delay must be equal to the variable time delay. As Tc is increased, however, the fixed delay Td also increases. Thus, to achieve a larger frequency range, a larger capacitance is required generating more circuit area and more input and dissipative power.
FIG. 2 shows a typical delay interpolating tuning ring oscillator 230. As the control voltage 262 changes, the delay interpolator 270 adds or interpolates the delay from two different delay paths 264 and 266. If the control voltage 262 chooses more of the N1 path 266 input, the frequency is increased. If the control voltage 262 chooses more of the N2 path 264 input, the frequency is decreased. Mathematically, the frequency of oscillation is: F=½[Td(K*N1+(1−K)*N2)]−1 where Td is the fixed time delay per stage, N1 is the equivalent number of delay stages for the short path 266, N2 is the equivalent number of delay stages for the long path 264, and K is an interpolation variable. As an example, if N1=3 and N2=5, and K varies between 0 to 1 based on the control voltage, the oscillation frequency varies by a factor of 5/3. Theoretically, however, the total frequency range cannot vary by more than 1.6:1 for a single interpolation stage.
FIG. 3 is a diagram of a known interpolative VCO provided in a star structure having an outer ring of main inverters and an inner sub-ring of inverters configured in a star formation. With the interpolative VCO 300 of FIG. 3, the inner sub-ring inverters 310-318 interpolate in phase with the main inverters 320-328 on the outside of the ring. In the known interpolative VCO 300 architecture, the external main ring inverter size is equal to the internal control path, or sub-ring path, inverter size. The stage number of the main loop is Y and the stage number of the internal sub-ring is X, where Y and X are odd numbered in the depicted example and Y is greater than X. In particular, in the depicted example, Y is 5 and X is 3.
As is generally known in the art, the term “size” is synonymous with “strength.” The “strength” of a path is proportional to the device W/L ratio. Normally L is set to the minimum channel length supported by the technology for the most area efficiency. Strength may also be considered in terms of current. For a device in saturation: I=½μCox W/L(Vgs−VT)2=½ gm(Vgs−VT) where gm=μCox W/L(Vgs−VT), and where VT is the threshold voltage, gm is the transconductance, Vgs is the gate-to-source voltage, W is the device width, L is the device length, Cox is the oxide capacitance, and μ is the mobility.
Returning to FIG. 3, the paths of the inner sub-ring inverters 310-318 are enabled by the application of a control voltage Vc of the VCO 300. The amount by which the inner sub-ring inverters 310-318 change the frequency of the outer ring inverters 320-328 is controlled by the amount of the control voltage Vc applied to the transistors 330-338. This control voltage may range from Vc=0 to Vc=Vdd. When Vc=Vdd, the interpolative VCO 300 may generate a maximum frequency. When Vc=0, the interpolative VCO 300 may generate a minimum frequency. However, it should be appreciated that in this known interpolative VCO 300 architecture, the ratio of maximum to minimum frequency is fixed to about 2.5. This is because the size of the inverters is fixed.